Hardware-Oriented

Frequency Response Analysis of Common Source MOSFET Amplifier

Aim

To design and set up a single-stage Common Source MOSFET amplifier with given specifications and plot the frequency response.
  1. Using LTspice Software simulation.
  2. Hardware implementation on bread board.

Apparatus & Software

ComponentQuantity
Function Generator1
DC Supply1
Oscilloscope1
MOSFET 2N70001
Bread Board1
Connecting Wires-
100 kΩ Resistor1
33 kΩ Resistor1
2.7 kΩ Resistor1
820 kΩ Resistor1
470 Ω Resistor1
1 µF Capacitor2
10 µF Capacitor1
Software: LTspice XVII (simulation using IRF1310 as equivalent model for 2N7000, with AC analysis directive: .ac dec 100 50 1e10).

Theory

A. MOSFET Overview
The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure has become the most important device in the electronics industry. It dominates integrated circuit technology in Very Large Scale Integration (VLSI) — both n-channel MOSFETs and Complementary MOSFET (CMOS) designs. MOSFETs are four-terminal devices with a source (S), gate (G), drain (D), and substrate/body (B). A thin layer of silicon dioxide (SiO₂) acts as an insulator between the gate and the channel, which is why MOSFETs are also known as Insulated Gate FETs (IGFETs).
In a MOSFET, current flows from the drain to the source through a semiconductor channel. The gate voltage controls the channel resistance and hence the drain current. MOSFETs can be n-channel or p-channel type, and either enhancement mode (normally OFF) or depletion mode (normally ON).
Enhancement mode MOSFET: Normally OFF (in cutoff, no current) when VGS = 0. Turns ON (saturation, conducting) when VGS exceeds the threshold voltage Vt. In an n-channel device, a positive gate voltage attracts electrons to the Si-SiO₂ interface and forms the conducting channel.
B. MOSFET Operating Regions
The MOSFET operates in three distinct regions depending on the terminal voltages:
  1. Cut-off region: VGS < Vt — No channel is formed; the device is OFF and ID ≈ 0.
  2. Linear (Triode) region: VGS > Vt and VDS < (VGS − Vt) — The channel exists throughout; the MOSFET acts like a voltage-controlled resistor.
  3. Saturation region: VGS > Vt and VDS > (VGS − Vt) — The channel is pinched off at the drain end. The drain current becomes approximately independent of VDS.
Pinch-off occurs when VDS = (VGS − Vt). For amplifier operation, the MOSFET must be biased in the saturation region to provide a large, approximately linear voltage gain. The drain current at the Q-point in saturation is:
ID=k′(VGS−Vt)2I_D = k'(V_{GS} - V_t)^2
where Vt is the threshold voltage and k' is a device parameter (related to carrier mobility and oxide capacitance).
C. Common Source Amplifier — Configuration and Biasing
In the Common Source (CS) configuration, the input signal is applied to the gate (VGS), and the output is taken from the drain terminal (VDS). The CS amplifier has the characteristic of high input impedance, which prevents it from loading the signal source. This high impedance is set by the bias resistors R1 and R2 — their values are chosen as large as possible, but not so large that the gate leakage current causes a significant bias voltage shift.
The gate voltage is established by a voltage divider (R1, R2) from VDD. The source resistor RS provides DC bias stability via negative feedback. The bypass capacitor CS short-circuits RS at AC frequencies, preventing signal degeneration and maximising AC gain.
D. AC Voltage Gain
The small-signal voltage gain of the CS amplifier (with RS fully bypassed by CS) is:
Av=−gm(RD∥RL)A_v = -g_m (R_D \| R_L)
The negative sign indicates phase inversion between input and output. The transconductance gm depends on the Q-point drain current:
gm=2k′(VGS−Vt)=2IDVGS−Vtg_m = 2k'(V_{GS} - V_t) = \frac{2I_D}{V_{GS} - V_t}
E. Frequency Response
The frequency response of a CS amplifier has three distinct regions: (1) Low-frequency region — gain rolls off because coupling capacitors (Cin, Cout) and the bypass capacitor CS have high impedance at low frequencies and do not fully pass/bypass signals; (2) Mid-band region — all capacitors act as short circuits and the gain is approximately flat; (3) High-frequency region — internal parasitic capacitances of the MOSFET (Cgs, Cgd) and Miller effect cause gain to roll off.
The gain in dB and the bandwidth are defined as:
Av,dB=20log⁡10(VoutVin)A_{v,dB} = 20 \log_{10}\left(\frac{V_{out}}{V_{in}}\right)
BW=fH−fLBW = f_H - f_L
where fL and fH are the lower and upper cutoff frequencies — the frequencies at which the gain drops by 3 dB from the mid-band value.

Pre-Lab / Circuit Diagram

The circuit uses a 2N7000 N-channel enhancement MOSFET with a voltage divider bias network. Component values: R1 = 100 kΩ, R2 = 33 kΩ, RD = 2.7 kΩ, RS = 470 Ω, RL = 820 kΩ, Cin = Cout = 1 µF, CS = 10 µF, VDD = 12 V.
Common Source MOSFET (2N7000) amplifier circuit diagram

Fig 1: Common Source MOSFET (2N7000) amplifier circuit with VDD = 12 V. R1 = 100 kΩ, R2 = 33 kΩ, RD = 2.7 kΩ, RS = 470 Ω, RL = 820 kΩ, Cin = Cout = 1 µF, CS = 10 µF.

Procedure

LTspice Simulation:
  1. Draw the CS amplifier schematic in LTspice using IRF1310 as an equivalent model for 2N7000 (2N7000 is unavailable in the LTspice library). Set VDD = 12 V, RD = 2.7 kΩ.
  2. Set the input signal source to SINE(0 0.2 1k) with AC amplitude 12 for the AC analysis.
  3. Set up an AC analysis directive: .ac dec 100 50 1e10 (decade sweep, 100 points/decade, from 50 Hz to 10 GHz).
  4. Run the simulation and plot V(out) in dB versus frequency to obtain the Bode plot.
  5. Use cursors to identify the peak mid-band gain, lower cutoff frequency (fL), and upper cutoff frequency (fH).
Hardware Implementation:
  1. Set up the circuit on a breadboard as per the circuit diagram: R1 = 100 kΩ, R2 = 33 kΩ, RD = 2.7 kΩ, RS = 470 Ω, RL = 820 kΩ, CC = 1 µF, CS = 10 µF, VDD = 12 V.
  2. Connect the function generator to the input (Vin) and the oscilloscope to both input and output terminals.
  3. Set the input signal to a sinusoidal wave at 1 kHz with an amplitude of 0.2 V.
  4. Vary the frequency of the input signal over a range of values (from 1 Hz to 2 MHz) and record the output voltage Vpp at each frequency step.
  5. Calculate the voltage gain and gain in dB at each frequency: Gain (dB) = 20 log₁₀(Vout / Vin).
  6. Plot gain (dB) vs log(frequency) to obtain the Bode plot. Mark the mid-band gain and the high and low frequency −3 dB cutoff points.

Simulation / Execution

The frequency response of the Common Source MOSFET amplifier was simulated in LTspice using the IRF1310 model as an equivalent substitute for the 2N7000 MOSFET. The AC analysis was run from 50 Hz to 10 GHz (.ac dec 100 50 1e10).
LTspice simulation showing peak mid-band gain

LTspice simulation — Peak gain identification: Cursor at 1.026 MHz shows peak gain of 17.92 dB. LTspice schematic uses IRF1310 (equivalent for 2N7000), with .ac dec 100 50 1e10 directive.

LTspice simulation showing bandwidth

LTspice simulation — Bandwidth identification: Cursor 1 at fH = 37.7 MHz (gain = 14.94 dB); Cursor 2 at fL = 33.6 kHz (gain = 14.97 dB). Both ≈ 15 dB, confirming −3 dB points from peak of ~18 dB.

From the LTspice simulation: Peak gain ≈ 17.92 dB at ~1 MHz. Lower cutoff fL ≈ 33.6 kHz; upper cutoff fH ≈ 37.7 MHz (both at ≈ 15 dB, i.e., midband − 3 dB). The observed variation in peak gain compared to hardware is attributed to the use of the IRF1310 model, which has different transconductance and parasitic capacitance characteristics than the actual 2N7000.

Observations

Below are oscilloscope captures showing the amplifier output at selected frequencies, illustrating the transition from low-frequency roll-off through the mid-band to high-frequency roll-off.
Oscilloscope output at 100 Hz

Oscilloscope — 100 Hz: Output Vpp = 2.88 V, Freq = 99.80 Hz. Low-frequency region — gain has not yet reached mid-band peak.

Oscilloscope output at 500 Hz

Oscilloscope — 500 Hz: Output Vpp = 3.68 V, Freq = 500.2 Hz. Near mid-band — gain approaching plateau.

Oscilloscope output at 50 kHz

Oscilloscope — 50 kHz: Output Vpp = 2.92 V, Freq = 50 kHz. High-frequency region — gain has rolled off from mid-band peak.

The following table records the output voltage (Vpp) and corresponding gain (dB) measured at various frequencies. Input Vin = 0.2 V.
Frequency (Hz)log fOutput Voltage Vpp (V)Gain (dB)
100.095-12.49
50.6990.25-4.08
1010.51.94
201.3981.269.97
351.5441.7512.82
501.6992.1614.65
10022.8817.15
2502.3983.4618.74
5002.6993.6819.28
7502.8753.7619.46
100033.7619.46
25003.3983.7619.46
50003.6993.7619.46
75003.8753.7219.37
1000043.7219.37
200004.3013.5618.99
330004.5193.2818.28
500004.6992.9217.27
750004.8752.4815.85
10000052.1614.65
2500005.3981.128.94
5000005.6990.5362.54
7500005.8750.384-0.35
100000060.3-2.50
20000006.3010.16-7.96
The frequency response shows a typical band-pass shape: gain increases in the low-frequency region, remains flat at ≈ 19.46 dB in the mid-band (750 Hz – 7.5 kHz), and rolls off at higher frequencies due to MOSFET parasitic capacitances.
Hardware Bode plot generated from readings

Bode plot (hardware): Gain (dB) vs log(frequency). Peak mid-band gain ≈ 19.46 dB.

Calculations

Mid-Band Gain (Hardware):
Av,mid=VoutVin=3.760.2=18.8  ⟹  20log⁡10(18.8)≈19.46 dBA_{v,\text{mid}} = \frac{V_{out}}{V_{in}} = \frac{3.76}{0.2} = 18.8 \implies 20\log_{10}(18.8) \approx 19.46\,\text{dB}
Bandwidth Identification (Hardware): The −3 dB level is at 19.46 − 3 = 16.46 dB, corresponding to Vout = 0.707 × 3.76 ≈ 2.66 V. From the gain table, this level is crossed at approximately fL ≈ 33 kHz (gain = 18.28 dB, falling) and fH ≈ 750 kHz (gain = −0.35 dB, fallen well below). Interpolating, fH lies between 500 kHz and 750 kHz.
BWhardware=fH−fL≈750 kHz−33 kHz=717 kHzBW_{\text{hardware}} = f_H - f_L \approx 750\,\text{kHz} - 33\,\text{kHz} = 717\,\text{kHz}
Bandwidth Identification (Simulation): From LTspice cursors — peak gain = 17.92 dB at 1.026 MHz; fL = 33.6 kHz at 14.97 dB; fH = 37.7 MHz at 14.94 dB (both ≈ peak − 3 dB = 14.92 dB ✓).
BWsimulation=fH−fL=37.7 MHz−33.6 kHz≈37.7 MHzBW_{\text{simulation}} = f_H - f_L = 37.7\,\text{MHz} - 33.6\,\text{kHz} \approx 37.7\,\text{MHz}

Results & Analysis

The single-stage Common Source MOSFET amplifier was successfully designed, implemented, and analysed. Key parameters determined from the experiment are summarised below.
ParameterHardware (Measured)LTspice Simulation
Mid-Band Gain (dB)≈ 19.46 dB≈ 17.92 dB
Lower Cutoff Frequency fL≈ 33 kHz≈ 33.6 kHz
Upper Cutoff Frequency fH≈ 750 kHz≈ 37.7 MHz
Bandwidth BW≈ 717 kHz≈ 37.7 MHz
  • The hardware and simulation results are in close agreement for mid-band gain (19.46 dB vs 17.92 dB) and lower cutoff frequency (~33 kHz in both).
  • The upper cutoff frequency differs significantly: ~750 kHz (hardware) vs ~37.7 MHz (simulation). This is primarily due to the use of IRF1310 (a high-current power MOSFET with different parasitic capacitances) as a substitute for 2N7000 in LTspice, which does not accurately model the high-frequency behaviour of the 2N7000 signal MOSFET.
  • The frequency response curve exhibits the expected band-pass shape with a well-defined flat gain region (mid-band) between 750 Hz and 7.5 kHz in hardware.

Conclusion

The single-stage Common Source MOSFET amplifier was successfully designed and analysed. Using LTspice, the frequency response was simulated with the IRF1310 model as a substitute for the 2N7000, yielding a peak gain of 17.92 dB, with fL ≈ 33.6 kHz and fH ≈ 37.7 MHz. The hardware implementation demonstrated a mid-band gain of 19.46 dB with fL ≈ 33 kHz and fH ≈ 750 kHz. The close agreement in mid-band gain and lower cutoff frequency validates the design, while the significant difference in upper cutoff frequency is attributed to the IRF1310 model substitution and associated parasitic parameter mismatch. The experiment provided a comprehensive understanding of MOSFET amplifier frequency-domain behaviour.

Post-Lab / Viva Voce

  1. Q: What is the role of the source bypass capacitor CS in a Common Source amplifier?

    A: CS is connected in parallel with RS. At DC, CS is open, so RS provides bias stability through negative feedback. At AC signal frequencies, CS acts as a short circuit (impedance 1/ωCS ≈ 0), bypassing RS and eliminating AC signal degeneration. This maximises the AC voltage gain. Without CS, the gain would be reduced by the factor (1 + gm·RS), making CS essential for achieving high gain in the mid-band.
  2. Q: What are the three operating regions of a MOSFET and which is used for amplification?

    A: The three operating regions are: (1) Cut-off (VGS < Vt) — no channel, no current; (2) Linear/Triode (VGS > Vt, VDS < VGS − Vt) — MOSFET acts as a voltage-controlled resistor; (3) Saturation (VGS > Vt, VDS > VGS − Vt) — drain current is approximately constant, ID ≈ k'(VGS − Vt)². For amplification, the MOSFET must be biased in the saturation region, where the drain current is a smooth, approximately linear function of VGS, enabling large voltage gain.
  3. Q: Why does the gain of a CS amplifier roll off at both low and high frequencies?

    A: At low frequencies, coupling capacitors (Cin, Cout) and bypass capacitor CS have high impedance and do not fully pass or bypass signals, causing gain reduction. At high frequencies, internal parasitic capacitances of the MOSFET (Cgs, Cgd) create feedback and loading that limit bandwidth. The Miller effectmiller effectThe multiplication of an inverting amplifier's feedback capacitance by the voltage gain, making it appear much larger at the input. It limits high-frequency performance. due to Cgd amplifies the effective input capacitance as Cin,eff = Cgd(1 + |Av|), forming a low-pass filter with the source resistance and causing high-frequency gain roll-off.
  4. Q: Define bandwidth and explain how it is measured from a Bode plot.

    A: Bandwidth (BW = fH − fL) is the range of frequencies over which the gain remains within −3 dB of the mid-band value. On a Bode plot, fL and fH are identified as the frequencies where the gain curve crosses the mid-band gain minus 3 dB. A wider bandwidth means the amplifier faithfully amplifies a broader range of frequencies. In this experiment, the hardware BW ≈ 717 kHz and simulation BW ≈ 37.7 MHz.
  5. Q: What is the voltage gain expression for a Common Source amplifier and what determines it?

    A: The small-signal voltage gain is Av = −gm(RD ∥ RL). The negative sign indicates phase inversion. The magnitude depends on the transconductance gm = 2k'(VGS − Vt) = 2ID/(VGS − Vt), which is set by the Q-point, and the effective drain load (RD ∥ RL). Increasing RD or gm increases gain, but this is limited by the DC operating point — a larger RD reduces VDS and can push the MOSFET out of saturation.
  6. Q: Why does the simulation result differ from the hardware measurement, particularly at high frequencies?

    A: The primary reason is the use of IRF1310 as a substitute for the unavailable 2N7000 model in LTspice. The IRF1310 is a high-current power MOSFET with significantly different parasitic capacitances (Cgs, Cgd) compared to the 2N7000 signal MOSFET. This causes the simulated upper cutoff frequency (37.7 MHz) to differ greatly from the hardware value (~750 kHz). Additional factors include component tolerances, breadboard parasitic capacitance, and oscilloscope probe loading.
  7. Q: What is the Miller effect and how does it impact the high-frequency response of a CS amplifier?

    A: The Miller effect refers to the multiplication of the feedback capacitance Cgd (gate-drain capacitor) by the voltage gain, creating a large effective input capacitance: Cin,eff = Cgd(1 + |Av|). This large capacitance forms a low-pass RC filter with the signal source resistance, limiting the high-frequency response. As gain increases, the Miller capacitance increases proportionally, causing a lower upper cutoff frequency. This is a fundamental trade-off: higher gain amplifiers have a narrower bandwidth, captured in the gain-bandwidth product (GBW = Av × BW ≈ constant).

References & Resources (Not Applicable)

This section is not required for this experiment.