Hardware-Oriented

Design and Implementation of 8:3 Encoder Circuit on FPGA Board

Aim

To design and implement an 8:3 encoder circuit on the FPGAfpgaField-Programmable Gate Array — an integrated circuit containing configurable logic blocks and programmable interconnects that can be reconfigured after manufacturing to implement custom digital circuits. board.

Apparatus & Software

S.No.	Tool / Equipment	Purpose
1	FPGA Development Board (Spartan-6)	Hardware implementation and verification
2	Xilinx ISE Software	HDL design entry, synthesis, and implementation
3	ISim Simulator	Functional simulation before hardware download
4	USB Programming Cable	Downloading bitstream to FPGA board
5	PC / Workstation	Running the Xilinx software environment

Theory

An encoder is a combinational circuit that performs the reverse operation of a decoder. It converts a set of binary inputs (typically in one-hot format) into a compact binary code at its outputs. It encodes the information from 2^n input lines into an n-bit binary output code representing the position of the active input.

An 8:3 encoder has 8 input lines (I0–I7) and 3 output lines (Y0–Y2). At any given time, exactly one input is assumed to be high, and the output Y[2:0] holds the 3-bit binary representation of the active input's index.

Limitations of a Standard Encoder: A standard encoder has two key limitations. First, if all inputs are 0, the output is undefined or ambiguous (typically defaults to 000, which conflicts with the encoding for I0=1). Second, if more than one input is simultaneously high, the output becomes incorrect because the circuit is designed for only one active input at a time. These problems are resolved by using a priority encoderpriority encoderA combinational circuit that outputs the binary code of the highest-priority active input when multiple inputs are asserted simultaneously., which assigns a priority to each input and generates the output corresponding to the highest-priority active input.

The truth table for the 8:3 encoder (assuming one-hot input) is given below:

Active Input	I7	I6	I5	I4	I3	I2	I1	I0	Y2	Y1	Y0
I0	0	0	0	0	0	0	0	1	0	0	0
I1	0	0	0	0	0	0	1	0	0	0	1
I2	0	0	0	0	0	1	0	0	0	1	0
I3	0	0	0	0	1	0	0	0	0	1	1
I4	0	0	0	1	0	0	0	0	1	0	0
I5	0	0	1	0	0	0	0	0	1	0	1
I6	0	1	0	0	0	0	0	0	1	1	0
I7	1	0	0	0	0	0	0	0	1	1	1

Pre-Lab / Circuit Diagram (Not Applicable)

This section is not required for this experiment.

Procedure

Open Xilinx ISE and create a new project targeting the appropriate FPGA device.
Create a new Verilog source file and write the 8:3 encoder module using an always block and a case statement that maps each one-hot 8-bit input to its corresponding 3-bit binary output. Add a default case for handling the all-zeros input condition.
Create the User Constraints File (UCF) mapping I[0]–I[7] and Y[0]–Y[2] to their designated FPGA pin locations.
Run the behavioural simulation in ISim by applying all 8 one-hot input combinations and verifying that the correct 3-bit binary output is produced.
Synthesize and implement the design in Xilinx ISE.
Generate the programming bitstreambitstreamThe binary configuration file downloaded to an FPGA that programs its internal logic blocks and routing interconnects to implement a specific design. and download to the FPGA board.
Test the four representative input cases on the board using toggle switches.
Observe the LED outputs for Y0, Y1, and Y2 and verify the binary encoding matches the active input index.

Simulation / Execution

Verilog Code for 8:3 Encoder Implementation:

verilog

module Encoder(
  input  [7:0] I,
  output reg [2:0] Y
);
  always@(I)
  begin
    case(I)
      8'b00000001: Y = 3'b000;
      8'b00000010: Y = 3'b001;
      8'b00000100: Y = 3'b010;
      8'b00001000: Y = 3'b011;
      8'b00010000: Y = 3'b100;
      8'b00100000: Y = 3'b101;
      8'b01000000: Y = 3'b110;
      8'b10000000: Y = 3'b111;
      default:     Y = 3'b111;
    endcase
  end
endmodule

In the code above, I and Y are bit-vectors (buses). The case statement assigns the appropriate 3-bit binary code to Y for each one-hot input combination. A default case is included to handle the condition when all inputs are zero — the output defaults to 3'b111 to avoid undefined behaviour.

User Constraints File for 8:3 Encoder:

properties

NET "I[0]" LOC="P22";
NET "I[1]" LOC="P21";
NET "I[2]" LOC="P17";
NET "I[3]" LOC="P16";
NET "I[4]" LOC="P15";
NET "I[5]" LOC="P14";
NET "I[6]" LOC="P12";
NET "I[7]" LOC="P11";
NET "Y[0]" LOC="P138";
NET "Y[1]" LOC="P143";
NET "Y[2]" LOC="P142";

Simulation Output: Waveforms for all 8 one-hot input combinations

Simulation waveform for 8:3 Encoder: output Y correctly encodes the binary index of the active input for all 8 one-hot input combinations.

From the simulation waveform, the output bits Yi exactly match the expected binary encoding for every one-hot input combination. It is verified that only one bit of I is high in each test case, ensuring correct encoder functionality.

Observations

Hardware implementation was verified on the FPGA board. Four representative input cases were tested.

Case	Active Input	Y2 (Obs.)	Y1 (Obs.)	Y0 (Obs.)	Binary Output	Expected Binary
1	I0 = 1, all others 0	0	0	0	000	000
2	I3 = 1, all others 0	0	1	1	011	011
3	I5 = 1, all others 0	1	0	1	101	101
4	I7 = 1, all others 0	1	1	1	111	111

Case 1 (I0=1, all others 0): Input I0 is high while all other inputs are low. The outputs Y0, Y1, and Y2 are all zero, which is the binary representation of the number 0.

Case 1: I0 active — Y[2:0]=000 (binary 0).

Case 2 (I3=1, all others 0): Input I3 is high. Outputs Y0 and Y1 are high while Y2 is low, giving the binary output 011, which is the binary representation of 3.

Case 2: I3 active — Y[2:0]=011 (binary 3).

Case 3 (I5=1, all others 0): Input I5 is high. Outputs Y0 and Y2 are high while Y1 is low, giving the binary output 101, which is the binary representation of 5.

Case 3: I5 active — Y[2:0]=101 (binary 5).

Case 4 (I7=1, all others 0): Input I7 is high. All outputs Y0, Y1, and Y2 are high, giving the binary output 111, which is the binary representation of 7.

Case 4: I7 active — Y[2:0]=111 (binary 7).

Calculations

Verification of binary output encoding for all four test cases:

Active Input Index	Expected Binary Y[2:0]	Decimal Verification
I0 (index 0)	000	0 in decimal — Y[2:0] = 0
I3 (index 3)	011	3 in decimal — Y[2:0] = 3
I5 (index 5)	101	5 in decimal — Y[2:0] = 5
I7 (index 7)	111	7 in decimal — Y[2:0] = 7

In all cases, the 3-bit binary output equals the decimal index of the active input, confirming correct encoder operation.

Results & Analysis

The 8:3 encoder was successfully designed in Verilog and implemented on the FPGA board.

Software Verification: The simulation results matched the truth table for all 8 one-hot input combinations.
Hardware Verification: The hardware implementation confirmed that the 3-bit binary output correctly encodes the index of the active input for all tested cases.

Conclusion

In this experiment, the implementation of an 8:3 encoder on the FPGA board was successfully completed. Both software simulation and hardware implementation were performed and verified against the expected truth table. The different problems that can arise in a standard encoder — such as undefined output when all inputs are zero and incorrect output when multiple inputs are active — were identified, and the default case in the Verilog code was used as a remedial measure. The experiment demonstrates the complementary relationship between encoders and decoders as fundamental combinational building blocks.

Post-Lab / Viva Voce

Q: What is an encoder, and how does it differ functionally from a decoder?

A: An encoder is a combinational circuit that converts a one-hot (or sparse) input into a compact binary code. It reduces 2^n input lines to n output lines, where the binary output represents the index of the active input. A decoder performs the reverse: it converts an n-bit binary input into a one-hot 2^n output, activating exactly one output line corresponding to the binary value. In short, the encoder compresses information (many to few), while the decoder expands it (few to many).
Q: What are the two main problems associated with a standard (non-priority) encoder?

A: The two main problems are: (1) All-zeros input ambiguity — when none of the inputs is high, the output defaults to 000, which is the same as the valid encoding for input I0 being active. This makes it impossible to distinguish between 'no input active' and 'I0 active'. (2) Multiple active inputs — if more than one input is simultaneously high, the encoder produces an incorrect output that may not correspond to any valid input encoding. These problems are resolved by using a priority encoder, which assigns priorities to inputs and always generates the output for the highest-priority active input.
Q: What is a priority encoder, and how does it differ from a standard encoder?

A: A priority encoder resolves the ambiguity of having multiple simultaneous active inputs by assigning a priority order to the inputs, typically with the highest index input having the highest priority. When multiple inputs are active, the output corresponds to the highest-priority active input, and lower-priority active inputs are ignored. Priority encoders often include an additional output — a valid bit — that is high when at least one input is active, distinguishing the all-zeros input state from the I0-only active state. Standard encoders assume that only one input is ever active at a time.
Q: How is an 8:3 encoder related to a 3:8 decoder in terms of function and implementation?

A: An 8:3 encoder and a 3:8 decoder are inverse functions of each other. If the output of an 8:3 encoder is fed as input to a 3:8 decoder, the decoder recovers the original one-hot input pattern (assuming no noise or errors). This complementary relationship makes them commonly used in communication systems for data encoding and decoding. In implementation, the decoder uses a case statement that maps binary codes to one-hot outputs, while the encoder's case statement maps one-hot inputs to binary codes — essentially the same structure with the lookup direction reversed.
Q: In the Verilog implementation of the encoder, why is a default case included in the case statement?

A: The default case is included to handle the condition when all inputs are zero (8'b00000000), which does not match any of the eight explicitly listed one-hot patterns. Without a default case, the Verilog synthesissynthesisThe process of converting an HDL description into a gate-level netlist that can be mapped to the target hardware's logic elements. tool would leave Y undefined for this input combination, which could lead to unpredictable or incorrect hardware behaviour. The default case assigns a known output value (3'b111 in this implementation) to prevent undefined states, even though this conflicts with the valid I7 encoding — a practical compromise for handling the otherwise undefined state.
Q: What is the significance of using bit-vector (bus) representation for inputs and outputs in the Verilog encoder code?

A: Using bit-vector representation (e.g., input [7:0] I, output reg [2:0] Y) allows the entire 8-bit input and 3-bit output to be treated as single grouped signals, simplifying the code compared to declaring 11 separate single-bit ports. The case statement can then directly compare the 8-bit input I to 8-bit binary constants, and assign a 3-bit output Y in a single statement. This makes the code more readable, compact, and structurally similar to the truth table, and also synthesizes efficiently to a LUT-based implementation.
Q: If an 8:3 encoder is cascaded with a 3:8 decoder, what is the expected output, and under what conditions would this fail?

A: If a one-hot 8-bit input is applied to the 8:3 encoder, the resulting 3-bit binary output is fed to the 3:8 decoder, which should recover the original one-hot pattern — only the same output line as the original active input should be high. This round-trip works correctly when exactly one input to the encoder is active at a time. It fails when: (1) all inputs are zero (the encoder defaults to 111, causing the decoder to activate Y7 instead of no output), or (2) multiple inputs are active (the encoder produces an incorrect binary code, causing the decoder to activate the wrong output line).