Hardware-Oriented

Design and Implementation of Full Subtractor Circuit on FPGA Board

Aim

To design and implement a full subtractor circuit on the FPGAfpgaField-Programmable Gate Array — an integrated circuit containing configurable logic blocks and programmable interconnects that can be reconfigured after manufacturing to implement custom digital circuits. board.

Apparatus & Software

S.No.Tool / EquipmentPurpose
1FPGA Development Board (Spartan-6)Hardware implementation and verification
2Xilinx ISE SoftwareHDL design entry, synthesis, and implementation
3ISim SimulatorFunctional simulation before hardware download
4USB Programming CableDownloading bitstream to FPGA board
5PC / WorkstationRunning the Xilinx software environment

Theory

A full subtractor is a combinational circuit that performs the subtraction of two 1-bit binary numbers while also taking into account a borrow-in bit from the previous bit position. It has three inputs: A (minuend), B (subtrahend), and Bin (borrow-in), and two outputs: Difference (D) and Borrow-out (Bout).
The Difference output is high when an odd number of inputs are high, which is identical to the XOR of all three inputs — the same expression as the Sum in a full adder. The Borrow-out is high when the minuend A is smaller than the effective subtrahend (B + Bin), indicating that a borrow must be taken from the next higher bit position.
The Boolean expressions for Difference and Borrow are:
Difference=A⊕B⊕Bin\text{Difference} = A \oplus B \oplus B_{in}
Bout=(A‾⋅B)+(B⋅Bin)+(Bin⋅A‾)B_{out} = (\overline{A} \cdot B) + (B \cdot B_{in}) + (B_{in} \cdot \overline{A})
The truth table for a full subtractor is given below:
ABBinDifferenceBout
00000
00111
01011
01101
10010
10100
11000
11111

Pre-Lab / Circuit Diagram (Not Applicable)

This section is not required for this experiment.

Procedure

  1. Open Xilinx ISE and create a new project targeting the appropriate FPGA device.
  2. Create a new Verilog source file and write the full subtractor module using the assign statement for Difference (XOR of all inputs) and Borrow (using AND-OR with complements).
  3. Create the User Constraints File (UCF) mapping the three input ports (a, b, c) and two output ports (Difference, Borrow) to the designated FPGA pin locations.
  4. Hardware Layout: Map `a` (minuend), `b` (subtrahend), `c` (borrow-in) to the toggle switches and `Difference`, `Borrow` to the LEDs.
  5. Run the behavioural simulation in ISim by applying all 8 input combinations and verifying the outputs match the truth table.
  6. Synthesize and implement the design in Xilinx ISE.
  7. Generate the programming bitstreambitstreamThe binary configuration file downloaded to an FPGA that programs its internal logic blocks and routing interconnects to implement a specific design. and download to the FPGA board.
  8. Test all six representative input combination cases using the toggle switches and observe the LED outputs.

Simulation / Execution

Verilog Code for Full Subtractor Implementation:
verilog
module FullSubtractor(
  input a,
  input b,
  input c,
  output Difference,
  output Borrow
);
  assign Difference = a ^ b ^ c;
  assign Borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
User Constraints File for Full Subtractor:
properties
NET "a"          LOC = "P22";
NET "b"          LOC = "P21";
NET "c"          LOC = "P17";
NET "Difference" LOC = "P29";
NET "Borrow"     LOC = "P27";
Note: The input c in the code represents the borrow-in (Bin). The Difference is computed using triple XOR, identical to the Sum in a full adder. The Borrow is computed using the complement of A with AND-OR expressions reflecting when a borrow must be generated.
Simulation Output: Waveforms for all 8 input combinations

Simulation waveform for Full Subtractor: outputs Difference and Borrow match the truth table for all 8 input combinations.

From the simulation waveform, the outputs Difference and Borrow exactly match the truth table. Borrow is high only when the minuend A is smaller than the effective subtrahend (B + Bin). When all inputs are 1, both outputs are also 1.

Observations

Hardware implementation was verified on the FPGA board. The following 6 representative cases were successfully captured and verified against the truth table.
Input (A B Bin)Difference (Obs.)Bout (Obs.)Expected Diff.Expected BoutStatus
0 0 00000Verified
0 1 01111Verified
0 1 10101Verified
1 0 01010Verified
1 0 10000Verified
1 1 11111Verified
Case 1: Inputs 000 -> Difference=0, Bout=0

Input 000: Difference=0, Bout=0

Case 5: Inputs 010 -> Difference=1, Bout=1

Input 010: Difference=1, Bout=1

Case 2: Inputs 011 -> Difference=0, Bout=1

Input 011: Difference=0, Bout=1

Case 3: Inputs 100 -> Difference=1, Bout=0

Input 100: Difference=1, Bout=0

Case 6: Inputs 101 -> Difference=0, Bout=0

Input 101: Difference=0, Bout=0

Case 4: Inputs 111 -> Difference=1, Bout=1

Input 111: Difference=1, Bout=1

Calculations

Verification of Boolean expressions for representative test cases:
Difference=A⊕B⊕Bin\text{Difference} = A \oplus B \oplus B_{in}
Bout=(A‾⋅B)+(B⋅Bin)+(Bin⋅A‾)B_{out} = (\overline{A} \cdot B) + (B \cdot B_{in}) + (B_{in} \cdot \overline{A})
ABBinDifferenceBout
0000⊕0⊕0 = 0(1·0)+(0·0)+(0·1) = 0
0110⊕1⊕1 = 0(1·1)+(1·1)+(1·1) = 1
1001⊕0⊕0 = 1(0·0)+(0·0)+(0·0) = 0
1111⊕1⊕1 = 1(0·1)+(1·1)+(1·0) = 1

Results & Analysis

The Full Subtractor experiment provided the following insights:
  • Implementation Verification: The Verilog module using `assign` statements was successfully synthesized and downloaded to the FPGA.
  • Truth Table Validation: All 8 input combinations were verified in simulation. The hardware test cases confirmed that the Difference output follows the XOR parity logic (similar to Full Adder Sum) and the Borrow output is generated correctly whenever the subtrahend exceeds the minuend.
  • Subtraction Logic: The experiment highlighted the role of the borrow bit in cascading subtraction operations across multiple bits.

Conclusion

In this experiment, the implementation of a full subtractor on the FPGA board was successfully completed. Both software simulation and hardware implementation were performed and verified against the respective truth table. Different cases that produce similar output combinations were identified. The experiment demonstrates that the Difference output expression is identical to that of the full adder Sum, while the Borrow expression uses the complement of the minuend A — highlighting the structural relationship between addition and subtraction in combinational arithmetic circuits.

Post-Lab / Viva Voce

  1. Q: What is the difference between a half subtractor and a full subtractor?
    A: Half subtractor handles 2 inputs (A, B) and no borrow-in. Full subtractor handles 3 inputs (A, B, Bin) to support multi-bit cascading.
  2. Q: Why is the Difference expression in a full subtractor identical to the Sum expression in a full adder?
    A: Both use XOR logic (odd parity) for the result bit. The difference lies only in the carry/borrow generation logic.
  3. Q: When does Borrow-out become high?
    A: When Minuend < Subtrahend (effectively). Boolean: `Bout = (~A&B) | (B&Bin) | (Bin&~A)`.
  4. Q: How is subtraction typically done in processors?
    A: Using 2's complement addition. A - B is equal to A + (~B + 1). This allows the same Adder hardware to perform subtraction.
  5. Q: Comparison of Adder vs Subtractor Truth Tables?
    A: Sum and Difference columns are identical. Carry and Borrow columns differ based on the majority vs borrowing logic.

References & Resources

Digital Electronics Lab Manual
Download Common Lab Manual (PDF)