Hardware-Oriented

Design and Implementation of Full Adder Circuit on FPGA Board

Aim

To design and implement a full adder circuit on the FPGAfpgaField-Programmable Gate Array — an integrated circuit containing configurable logic blocks and programmable interconnects that can be reconfigured after manufacturing to implement custom digital circuits. board.

Apparatus & Software

S.No.	Tool / Equipment	Purpose
1	FPGA Development Board (Spartan-6)	Hardware implementation and verification
2	Xilinx ISE Software	HDL design entry, synthesis, and implementation
3	ISim Simulator	Functional simulation before hardware download
4	USB Programming Cable	Downloading bitstream to FPGA board
5	PC / Workstation	Running the Xilinx software environment

Theory

A full adder is a combinational arithmetic circuit with three inputs and two outputs, used to add binary numbers with more than 1 bit. The three inputs are the two current bits to be added (A and B) and a carry-in bit (Cin) from the addition of the previous bit position. The two outputs are the Sum bit and the Carry-out bit (Cout), which serves as the carry-in for the next higher bit position.

The Sum output is high when an odd number of the inputs are high, which is equivalent to the XOR of all three inputs. The Carry-out is high when two or more inputs are high, which is the majority function of the three inputs.

The Boolean expressions for Sum and Carry are:

\text{Sum} = A \oplus B \oplus C_{in}

C_{out} = (A \cdot B) + (B \cdot C_{in}) + (C_{in} \cdot A)

The truth table for a full adder is given below:

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Pre-Lab / Circuit Diagram (Not Applicable)

This section is not required for this experiment.

Procedure

Open Xilinx ISE and create a new project targeting the appropriate FPGA device.
Create a new Verilog source file and write the full adder module using the assign statement for Sum (XOR of all inputs) and Carry (majority function).
Create the User Constraints File (UCF) mapping the three input ports (a, b, c) and two output ports (Sum, Carry) to the designated FPGA pin locations.
Hardware Layout: Typically, map `a`, `b`, `c` to the rightmost toggle switches and `Sum`, `Carry` to the adjacent LEDs.
Run the behavioural simulation in ISim by applying all 8 input combinations and verifying the outputs match the truth table.
Synthesize and implement the design in Xilinx ISE.
Generate the programming bitstreambitstreamThe binary configuration file downloaded to an FPGA that programs its internal logic blocks and routing interconnects to implement a specific design. and download to the FPGA board.
Test all relevant input combinations using the toggle switches and observe the LED outputs.

Simulation / Execution

Verilog Code for Full Adder Implementation:

verilog

module Fulladder(
  input a,
  input b,
  input c,
  output Sum,
  output Carry
);
  assign Sum   = a ^ b ^ c;
  assign Carry = (a & b) | (b & c) | (c & a);
endmodule

User Constraints File for Full Adder:

properties

NET "a"     LOC = "P22";
NET "b"     LOC = "P21";
NET "c"     LOC = "P17";
NET "Sum"   LOC = "P29";
NET "Carry" LOC = "P27";

Simulation Output: Waveforms for all 8 input combinations

Simulation waveform for Full Adder: outputs Sum and Carry match the truth table for all 8 input combinations.

From the simulation waveform, the outputs Sum and Carry exactly match the expected outputs from the truth table. Initially all inputs are set to 0 and both outputs are low. Carry is high only when more than one input is high. When all inputs are 1, both outputs are also 1.

Observations

Hardware implementation was verified on the FPGA board. Four representative cases were tested to cover all key output scenarios.

Case	A	B	Cin	Sum	Cout	Expected Sum	Expected Cout
1	0	0	0	0	0	0	0
2	0	0	1	1	0	1	0
3	1	1	0	0	1	0	1
4	1	1	1	1	1	1	1

Case 1: Inputs 000 — Sum=0, Cout=0.

Case 2: Inputs 001 — Sum=1, Cout=0.

Case 3: Inputs 110 — Sum=0, Cout=1.

Case 4: Inputs 111 — Sum=1, Cout=1.

Calculations

Verification of Boolean expressions for all four test cases:

\text{Sum} = A \oplus B \oplus C_{in}

C_{out} = (A \cdot B) + (B \cdot C_{in}) + (C_{in} \cdot A)

A	B	Cin	Sum	Cout
0	0	0	0⊕0⊕0 = 0	0+0+0 = 0
0	0	1	0⊕0⊕1 = 1	0+0+0 = 0
1	1	0	1⊕1⊕0 = 0	1+0+0 = 1
1	1	1	1⊕1⊕1 = 1	1+1+1 = 1

Results & Analysis

The Full Adder design yielded the following observations:

Logic Verification: The Sum output correctly followed the parity of the inputs (XOR operation), identifying odd numbers of high inputs.
Carry Generation: The Carry output correctly identified when two or more inputs were high, satisfying the majority function.
Consistency: Hardware results for all 8 input combinations (represented by the 4 key cases above) were consistent with the specific boolean equations derived from the truth table.

Conclusion

This experiment bridged the gap between boolean algebra and arithmetic circuits. By implementing the Full Adder, we demonstrated how potentially complex arithmetic operations (like multi-bit addition) can be broken down into fundamental logic gates (XOR, AND, OR) and realized physically on an FPGA.

Post-Lab / Viva Voce

Q: What is the difference between a half adder and a full adder?
A: A half adder adds two bits and produces Sum and Carry but has no Carry-in input. A full adder adds three bits (A, B, Cin) and handles the carry from a previous stage.
Q: How can a 4-bit ripple carry adder be built using full adders?
A: By cascading four full adders. The Cout of each stage is connected to the Cin of the next stage. The LSB Stage has Cin=0.
Q: Why is XOR used for Sum and AND-OR used for Carry?
A: XOR (odd function) naturally implements binary addition sum logic (1+0=1, 1+1=0). The AND-OR structure implements the Majority logic required for a carry bit.
Q: What is the significance of Cout in a multi-bit adder?
A: Cout propagates the overflow to the next bit position. Ignoring it in the MSB results in an overflow error if the sum exceeds the bit-width capacity.
Q: What are the outputs when all inputs are 1?
A: Inputs 1, 1, 1 result in Sum=1 and Cout=1 (Binary 11, Decimal 3).